CMOS (complementary metal-oxide semiconductor) image sensors (CIS) used in smartphones and other multi-purpose devices typically support various formats of videos and high-resolution videos such as 4k/2160p (3840×2160 resolution), 1080p (1920×1080 resolution), and 720p (1280×720 resolution) at 30 frames per second (fps), 60 fps, 120 fps, 240 fps, and/or other frame rates and resolutions. Due to the limitations of a CIS readout circuit speed, data transmission speed, and storage requirements, higher frame-rate videos are typically down-sampled from a full frame or a selected sub-frame of the CIS. Common down-sampling ratios include one-half vertical, one-half horizontal (V:½, H:½) and one-third vertical, one-third horizontal (V:⅓, H:⅓), although other down-sampling ratios are possible.
Current CMOS image sensor (CIS) designs use column parallel ADC architectures. In a down-sampling readout, the speed (e.g., frame rate) is in general inversely proportional to the number of rows to be read, but not proportional to the number of columns to read, as current CIS include column ADCs for the array of pixels (or pixel elements) and therefore read times are limited by the row (or line) times and analog-to-digital conversion time and not affected by the number of columns. Current CIS utilize only a portion of the column parallel ADC architectures during a down-sampling read operation.
During a down-sampling readout operation, a portion of the columns and the rows are not read. For example, in a (V:½, H:½) down-sampling, only half of the rows and half of the columns in the CIS are sampled. In current CIS designs, when a column is skipped during a down-sampling operation, the column ADCs coupled to the skipped columns are not used. For a (V:½, H:½) down-sampling, only half of the column ADCs are currently utilized. For a (V:⅓, H:⅓) down-sampling, only a third of the column ADCs are currently utilized.